As a result of the steadily increasing integration density of semiconductor devices, photolithographic masks or templates for nanoimprint lithography have to transfer smaller and smaller features. To meet this demand, the actinic wavelength of the imaging tool has been reduced in steps of 436 nm and 365 nm to 193 nm. Furthermore, immersion lithography has been introduced to enlarge the numerical aperture of the projection systems. As a consequence, the mask manufacturing process has reached a very high degree of complexity accompanied with strongly enlarged costs. In the near future, reflective masks will be used for imaging using light of a wavelength of 13.5 nm.
Therefore, photolithographic mask blanks have to fulfil very tight specifications for transmission and reflection homogeneity, planarity, glass pureness and temperature expansion coefficient. In order to manufacture photolithographic masks with a sufficient yield, mask defects are removed by repair at the end of the manufacturing process. Nowadays even inadequate critical dimension (CD) and registration control parameters are corrected by innovative to post mask manufacturing techniques. Such correction methods are described in the U.S. provisional applications U.S. 61/351,056, U.S. 61/363,352 and U.S. 61/389,382 of the applicant, which are hereby incorporated herein in their entirety by reference.
The manufacturing process of integrated circuits requires a recurring application of a plurality of photolithographic masks, which is called a mask set. The mask set of an advanced semiconductor device can comprise up to 30 photolithographic masks. The mask transfer process by the exposure tool has to insure a perfect overlay of the printed resist features to the features patterned in preceding lithographic processes. A bad overlay can have serious impact on the chip yield, hence on the manufacturing costs.
The control of the overlay is therefore one of the critical processes in the integrated circuit (IC) manufacturing. In the following, the term microscopic device or simply device is used for all devices fabricated on semiconducting wafers, such as ICs, micro-electromechanical systems (MEMS) including sensors, detectors and displays and photonic integrated circuits (PICs) including lasers and photodiodes.
The term overlay describes the accuracy of placing features of two succeeding lithographic processes on top of each other. Overlay measurements are performed at specifically designed overlay targets, which are placed within the active area of the mask, and which are transferred together with the IC feature to contents. Typical overlay targets are box-in-box or bar-in-bar feature arrangements. The overlay error measurement is performed with specifically constructed optical tools, which are capable to determine the offset of the center of gravity of layer targets printed consecutively on top of each other.
DE 10 2006 054 820A1 and U.S. 61/363,352 disclose a method to correct residual pattern placement errors of photolithographic masks. This process is denoted as registration correction (RegC) process. It is based on irradiating the quartz carrier or the quartz substrate of a mask with light pulses of a femtosecond laser. Mask residual errors cannot be removed by linear correction such as field magnification, translation and field rotation adaptations of the scanner and stepper, respectively. The residual mask placement error correction is performed by writing a placement error distribution dependent density of laser pulses, also called pixel density. Writing the pixels results in a small local lateral expansion of the quartz carrier, hence in a reduction of the placement errors in case of an appropriately determined pixel density distribution.
A mathematic-physical model to determine the appropriate pixel distribution is described in U.S. provisional application 61/363,352. It further demonstrates the opportunity of doing both, mask transmission uniformity and pattern placement accuracy improvements.
Presently, as described in the above mentioned documents, the correction of pattern placement errors is separately performed for each photolithographic mask of a set of masks, i.e. independent from placement errors on other masks of the same mask set. In more detail, the pattern placement errors of each mask or of each template are corrected relative to a virtual optimum, which is given by an orthogonal coordinate system, determined from the position of the alignment marks on the mask, or alternatively by a root-mean-square based optimization process of the pattern placement errors determined in the active area of the mask. The minimization of overlay errors by individually correcting the pattern placement errors of each mask relative to this virtual optimum is a complex and thus time consuming process. In particular, the correction of displacement vectors having large magnitudes is difficult to perform using the RegC process and may additionally newly introduce further errors in the substrate of the respective mask.
Moreover, this procedure may not be optimal for minimizing the contribution of the individually corrected photolithographic masks of the mask set to the overlay error on the wafer, as the pattern placement errors of different photolithographic masks of the mask set are considered isolated from the other members of the mask set.
It is therefore one object of the present invention to provide a method and an apparatus for minimizing overlay errors to avoiding at least in part the above mentioned problems.